Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
نویسندگان
چکیده
منابع مشابه
Evolving Optimal Multi-Objective Hardware Using Strength Pareto Evolutionary Algorithms
In this paper, we focus on engineering Pareto-optimal digital circuits given the expected input/output behaviour with a minimal design effort. The design objectives to be minimised are: hardware area, response time and power consumption. We do so using the Strength Pareto Evolutionary Algorithms. This is novel application of multi-objective optimisation to circuit design. The performance and qu...
متن کاملAn Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms
One of the most important problems in SOC platforms design is that of defining strategies for tuning the parameters of a parameterized system so as to obtain the Pareto-optimal set of configurations that provide multi-criteria optimisation. The paper proposes a methodology based on evolutionary techniques for exploration of the range of possible configurations of a parameterized system [1]. A h...
متن کاملFinding Optimal Hardware Configurations For C Code
To look at a piece of C code especially an uncommented one is often not very enlightening. Even small pieces of code with one or two functions will often appear to perform the same array initializations, loops over the data, and basic arithmetic functions, without clearly indicating what the overall purpose of the routine is. This can be frustrating to those using the code as part of a package ...
متن کاملSearching for Pareto-optimal Randomised Algorithms
Randomised algorithms traditionally make stochastic decisions based on the result of sampling from a uniform probability distribution, such as the toss of a fair coin. In this paper, we relax this constraint, and investigate the potential benefits of allowing randomised algorithms to use non-uniform probability distributions. We show that the choice of probability distribution influences the no...
متن کاملPareto Optimal Modeling for Efficient PLL Optimization
Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each complete circuit solution candidate is prohibitive inside a numerical optimization loop. In this paper, we show how to circumvent this problem with a ca...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IPSJ Transactions on System LSI Design Methodology
سال: 2012
ISSN: 1882-6687
DOI: 10.2197/ipsjtsldm.5.133